Field of the Invention
The present invention relates to a semiconductor device.
Description of the Background Art
Conventionally, there is a known technique for effectively utilizing an area that can be used on a semiconductor chip by arranging some of elements in a corner of a semiconductor chip.
For example, Japanese Patent Laying-Open No. 2004-327538 discloses a semiconductor chip including an ESD (Electronic Static Discharge) protection element arranged in a corner of a chip sandwiched between IO regions (input/output regions).
Japanese Patent Laying-Open No. 2010-010168 discloses a semiconductor chip including an oscillation circuit arranged in a corner of a chip sandwiched between IO regions.
Japanese Patent Laying-Open No. 05-121650 discloses a semiconductor chip including a reference voltage generation circuit arranged in each of four chip corner regions.
Japanese Patent Laying-Open No. 2010-258298 discloses that a memory circuit, an electric fuse, an analog circuit, a CPU, a logic circuit, a power supply circuit, an ESD protection terminal, a standard cell, and the like are arranged in a circuit core arrangement region at a corner portion of a semiconductor chip.